IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Events - 2005
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December
On-chip Adaptive Components for Low-Power High-Performance Multimedia Processing
TACT, VSI, and IEEE CAS Society Bangalore Chapter jointly announce a
Technical Seminar
Speaker: Dr Rama Sangireddy, University of Texas, Dallas
Date: Dec 28, 2005
Time: 10.30 AM - 11.30 AM
Venue: TI Bangalore Auditorium

Workshop on VLSI Physical Design Automation
December 19-21, 2005
Hotel Atria, Bangalore India
Organized by: VLSI Society of India
In cooperation with: IEEE Solid State Circuits Society and IEEE Circuits and Systems Society, Bangalore Chapter
Conducted by: Dinesh Bhatia, University of Texas at Dallas

Tutorial on Source Coding
Technical Seminar
TACT and IEEE Circuits and Systems Society Bangalore Chapter
Speaker: Ajit Rao, TI India
Date: December 8, 2005
Time: 4.00 pm - 6.00 pm
Venue: TI Bangalore Auditorium

A Two-day Workshop on VLSI Signal Integrity
December 16 - 17, 2005
Hotel Atria, Bangalore
Organized by VLSI Society of India
In cooperation with: IEEE Circuits and Systems Society, Bangalore Chapter
Speakers:
Dr. Ram Achar, Carleton University, Canada; Dr. Ashok Balivada, Analog Devices, India; Dr. Shabbir Batterywala, Synopsys, India; Arvind, Texas Instruments India, and Dr. C.P. Ravikumar, Texas Instruments India.

Design for Testability - Theory and Practice
A Three-day Intensive Course
December 15 - 17, 2005 IIT New Delhi, India
Organized by VLSI Society of India
In cooperation with: IEEE Circuits and Systems Society
Instructors:
Dr.Vishwani D. Agrawal, Auburn University and Dr.C.P. Ravikumar, Texas Instruments India

November
Technical Talk
Sponsored by IEEE CAS Society, Bangalore and TACT, TI
Speaker: Prof. M.N.S. Swamy, Concordia University, Canada
Date: November 30, 2005 (Wednesday)
Time: 4.00 pm – 5.30 pm
Venue: TI Bangalore Auditorium

First Workshop on Design Verification Methodologies
November 25, 2005, Hotel Atria, Bangalore, India
Organized by: VLSI Society of India
In cooperation with: Design Verification Forum - India, IEEE Circuits and Systems Society, Bangalore Chapter
Speakers:
Mahesha Puttanna, Wipro Technologies; Srinivasan Venkataramanan, Synopsys, India; Badri Gopalan, Ageia Technologies; Venkatesan Swaminathan, Intel, Bangalore; Vinaya Singh, Cadence Design Systems; Sundaresan Kumbakonam, Broadcom, and Venkatesh Natarajan, Texas Instruments India.

September
From ESL to Implementation: Chip Design in Half the Time Using Bluespec SystemVerilog
Sponsored by TACT, VSI and IEEE CAS Bangalore Chapter
Technical Talk by
Sathyam K. Pattanam, VP Engineering, Bluespec
Date: Sep 8, 2005 (Thursday)
Time: 10.30 AM – 12.30 PM
Venue: TI Bangalore Auditorium

August
Design For Testability - What is it and How did we get here?
TACT, VLSI Society of India, and IEEE CAS Bangalore Chapter announce a
Seminar by
T. W. Williams, Synopsys Fellow
Date: Aug 16, 2005 (Tuesday)
Time: 11.00 AM – 12.00 Noon, Tea at 10.45 AM
Venue: TI Bangalore Auditorium

9th IEEE VLSI Design & Test Symposium VDAT2005
August 10-13, 2005
Wipro Technologies, Electronics City, Bangalore, India
Organized by: VLSI Society of India
Industry Sponsors: TI India, Wipro Technologies and Intel India
In Cooperation With: IEEE EDS/SSCS, IEEE CAS Bangalore Chapter and IEEE-CS-TTTC

July
4-day Intensive Course on Design for Testability – Theory and Practice
July 27-30, 2005
Venue: Hotel Atria, Bangalore, India
Organized by: VLSI Society of India
Corporate Sponsor: Tessolve, India
In co-operation with: IEEE Circuits and Systems Society, Bangalore Chapter and IEEE-CS-Test Technology Technical Council (TTTC)
Instructors:
Dr.Vishwani D.Agrawal and Prof.Adit D.Singh (Auburn University)

Recent Advances in Coding Theory
IEEE CAS Bangalore Chapter and TACT present
Seminar by
Krishna R. Narayanan, Associate Professor
Dept. of Electrical Engineering
Texas A&M University, College Station
Date: 25-7-2005 (Monday)
Time: 4.00 – 5.00 PM
Venue: TI Bangalore Auditorium

2nd VLSI Embedded Systems DSP Applications Seminar
VEDAS 2005
JULY 1-2, 2005
Venue: Sona College of Technology, Salem, Tamilnadu, India
Sponsored by: VLSI Society of India, Cadence, Analog Devices, Texas Instruments India
Organized by: PSG College of Technology, Coimbatore
In Co-operation with: IEEE Circuits and Systems Society, Bangalore, and IEEE Student Chapter, SCT and TTTC
Speakers:
V Kamakoti, IIT Madras; Srinivasan Venkataraman, Synopsys; N.J.R. Muniraj, Sona College of Technology; Navkanta Bhat, IISc,Bangalore; C. P. Ravi Kumar, Texas Instruments; Rahul Kumar, National Semiconductors; Vishal Dalal, Sasken; Soujana Sarkar, Texas Instruments; V. Ranganathan, Sathyam, Chennai, and Chandravel Sankarakumar, Sanmina,Bangalore

June
Custom LSI Design Workshop
Manipal, Karnataka
June 6-18, 2005
Sponsored by: VLSI Society of India and KarMic (Karnataka Micro Electronics, Manipal, Karnataka)
In cooperation with: IEEE Circuits and Systems Society, Bangalore Chapter

May
The Future of Analog ICs
Sponsors: TACT, VLSI Society of India, and The IEEE Circuits and Systems Society, Bangalore Chapter
The seminar will present an expert’s views on the future of Analog ICs
Speaker: Prof. T.R. Viswanathan, Professor, UT Dallas
Date: May 19, 2005 (Thursday)
Time: 5.00 PM – 6.00 PM
Venue: TI Bangalore Auditorium

April
Introduction to Sigma Delta Converters
Technical talk and Chapter meeting
Sponsored by: IEEE Circuits and Systems Society, Bangalore Chapter
Speaker: Dr. P.V. Ananda Mohan (ECIL)
Date: April 26, 2005
Time: 5.00 PM – 6.00 PM
Venue: TI Bangalore Auditorium

February
Workshop on Low Power Design Techniques
February 25-26, 2005
Golden Jubilee Hall, ECE Dept, IISc - Bangalore
Sponsor: VLSI Society of India
In cooperation with: IEEE Circuits and Systems Society (Bangalore Chapter), and IEEE Electron Devices and Solid State Circuits Society
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