IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Events - 2010
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November
Analog System Design
In cooperation with IEEE Bangalore Section, IEEE Circuits and Systems Society Bangalore Chapter, and VLSI Society of India, Texas Instruments India University Program announces a Five-day Faculty Development Program
Date: November 15-19, 2010
Time: 9.00 PM - 5.30 PM      Download announcement (PDF 54 KB)
Venue: TR-1, Texas Instruments India; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
The workshop is intended for faculty members actively engaged in teaching Analog Design/ Embedded Systems. Please register before Oct 15th. Registration can be done through e-mail by contacting Mr. Sagar Juneja (sagar.juneja@ti.com). Your participation will be confirmed.
October
Switched Mode Power Converters: DC – DC Converters
In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, and VLSI Society of India, PragaTI (TI India Technical University) announces a Two-day shortcourse
Speaker: Prof. Lakshminarasamma, Dept of Electrical Engg, IIT Chennai
Date: October 6-7, 2010
Time: 9.00 PM - 5.30 PM      Download announcement (PDF 288 KB)
Venue: TR-1, Texas Instruments India; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
Please arrive by 8.30 AM and carry photo identification. Limited parking is available for visitors.

Overview: There is a growing interest in energy harvesting and power management in integrated circuits. VLSI Society of India is organizing an introductory course on switched-mode power converters (DC-DC converters) for the benefit of practicing engineers. The course will also be useful to faculty and students. Please note that this course is not intended for Power Engineering professionals/faculty.

About the speaker: Prof. Lakshmi obtained her Ph.D. degree in Electrical Engineering from the Indian Institute of Science and joined the faculty of Electrical Engineering at the Indian Institute of Technology, Madras as an Assistant Professor. She has coauthored four journal papers in peer-reviewed journals, including the IEEE Transactions on Power Electronics and several premier conferences. Her research interests are in the areas of
• Power Electronics and drives
• Switched Mode Power converters
• Resonant converters


Guessing a Random Pass-Key
In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, and VLSI Society of India, PragaTI (TI India Technical University) announces a seminar
Speaker: Prof. Rajesh Sundaresan
Date: October 1, 2010
Time: 3.00 PM - 4.30 PM      Download announcement (PDF 29 KB)
Venue: TR-1, Texas Instruments India; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
Registration: There is no registration fee to attend the seminar, but registration is mandatory. Those who wish to attend must register at http://vlsi-india.org/vsi/activities/reg.shtml no later than September 30, 2010. Please arrive by 2.30 PM and carry photo identification. Limited parking is available for visitors.

Overview: Some results on the effort needed to guess a random pass-key will be discussed. They have applications in the analysis of the strength of secret-key crypto-systems against guessing attacks. The expected number of guesses needed before success grows exponentially with the length of the key-string. The goal will be to characterize the growth rate exponent. The problem of guessing is closely related to compression. After a brief discussion on this connection, some elementary results from large deviations theory will be used to identify the growth rate exponent. The session will be concluded with a discussion on an asymptotically optimal randomized attack.


July
High Frequency Characterization of Transistors
IEEE Circuits and Systems Society, Bangalore Chapter, in cooperation with VLSI Society of India and PragaTI (TI India Technical University) announces a seminar
Speaker: J. Prasad (DSM Solutions Inc, Los Gatos, CA)
Date: July 29, 2010
Time: 3.00 PM - 4.00 PM      Download announcement (PDF 56 KB)
Venue: TR-1, Texas Instruments India; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
Registration: There is no cost associated with this seminar, but registration is mandatory since seating is limited. Those who wish to attend must register at http://vlsi-india.org/vsi/activities/reg.shtml no later than July 27, 2010. Your participation will be confirmed and further instructions will be sent. Please arrive by 2.30 PM and carry photo identification. Limited parking available for visitors.

Overview: Most of the device and process engineers spend a lot of time looking at the D.C parametric data to make sure the device will be functional. They rarely find time to study the A.C parameters. At best, they look at the 1MHz capacitance data from large structures to get an estimate of the device capacitance. Ring oscillator data collected from a frequency counter attached to the D.C parametric tester gives a glimpse of the gate delay for logic circuits. However, for analog applications, additional measurements are needed. At this point, the wafers are thrown on the "other side of the wall" where the microwave engineers do the high-frequency characterization of the device. Quite often, the buzzwords, lingo and the vocabulary of the microwave engineers completely obscure the device engineers. This talk will describe what is happening "behind the scenes" in the high-frequency lab.
This talk will briefly introduce you to S-parameters, the vector network analyzer, calibration and de-embedding using the test structures. The device figures of merit Ft and Fmax will be described. The effect of load and source impedance on the stability of the device and stability factor will be will be discussed. The various power gains, Mason's Gain (U), Maximum Available Gain (MAG) and Maximum Stable Gain (MSG) and its effect on Fmax will be shown. We will show how to extract Ft and Fmax from the measured S-parameters. The measured S-parameters will also help us in developing a high-frequency model for the device.

About the speaker: Prasad obtained his Ph.D in Electrical Engineering from Oregon State University, Corvallis. Currently, he is a Director of Device Technology at DSM Solutions (Deep Sub Micron) where he has been working on 0.6V, 60nm complementary JFET technology for low power logic applications. For the past twenty-four years, he has been engaged in developing high-speed GaAs and SiGe HBT technology. He has been with Tektronix for 12 years developing GaAs-based HBT technology for high-speed oscilloscopes. He was a Tektronix Fellow and he was the first in the world to demonstrate a 60GHz InGaP HBT IC technology. During the last 12 years, he has been with National Semiconductor, Micrel Semiconductor and Maxim Integrated Products where he has developed SiGe BiCMOS processes for wireless and fiber optic applications, which have resulted in several products. Prior to the HBT work, Prasad has developed E2PROM processes at National Semiconductor and contributed to VMOS processes at AMI Semiconductor. Prasad is an IEEE Fellow and a Distinguished Lecturer of IEEE Electron Devices Society.
He is a member of the IEEE technical committees on Compound Semiconductor Devices, Compact Modeling and Education. He is currently serving in the IEEE Technical Field Awards and Fellow Committees. Prasad has been serving in the technical committees of BCTM and IEDM. Prasad was an Adjunct Professor at Oregon State University. He was also an adjunct faculty at Santa Clara University.


June
Solar Photovoltaic (SPV) System Design and Installation Orientation Program
A one-day hands-on workshop on, Organized by VLSI Society of India; In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, and PragaTI (TI India Technical University)
Speaker: Dr.Ashok Rao
Date: 24 June 2010
Time: 9:00 am - 5:30 pm      Download announcement (PDF 95 KB)
Venue: Texas Instruments India, Bagmane Tech Park, C.V. Raman Nagar, Bangalore 560093
Those who wish to attend this workshop must register at VLSI Society of India website compulsorily. Please refer the PDF workshop announcement for registration tariff.

About the program: There is increased awareness today about the perils of global warming and e-waste. Worldwide, we have witnessed the emergence of widespread interest in developing technologies that can reduce or eliminate the dependence on conventional sources of energy. Researchers and developers are looking at solar, wind, wave, and other alternate sources of to meet the growing energy needs of mankind. This one-day hands-on program is intended for professionals as well as academicians who are interested in getting exposed to the challenges of harnessing solar energy for energizing electrical and electronics appliances. The workshop will focus on the utilization of Solar Photovoltaic (SPV) power in small-scale applications.

Dr.Ashok RaoAbout the speaker: The workshop will be conducted by Dr.Ashok Rao, former Head of the Network Project in the Center for Electronic Design Technology, Indian Institute of Science. Ashok Rao obtained a Ph.D in Electrical Engineering from IIT Bombay and has a teaching and research experience of over 25 years. He is a trained SPV system design specialist, having been trained by Siemens Solar, California. During the lab session, he will be assisted by engineers from SELCO Solar Lighting Pvt Ltd, Bangalore, a leading Solar Lighting company in the world.


May
Low-Power Receiver Architecture and Algorithms for Wireless Personal Area Networks (WPAN)
A seminar Conducted by PragaTI (TI India Technical University), In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, and VLSI Society of India
Speaker: Satyam Dwivedi (Indian Institute of Science, Bangalore)
Date: 6 May 2010
Time: 3.30PM - 5.00PM      Download announcement (PDF 74 KB)
Venue: TR-1, Texas Instruments India, Bagmane Tech Park, C.V. Raman Nagar, Bangalore 560093
There is no cost associated with this seminar, but registration is mandatory since the seating is limited. Those who wish to attend this seminar must send a mail to Utsav Singh (x0129503@ti.com) no later than May 3, 2010. Your participation will be confirmed and further instructions will be sent. Please arrive by 3.00 PM and carry photo identification. Limited parking is available for visitors.

Abstract: This talk is on low-power receiver architecture and algorithms for IEEE 802.15.4 WPAN, which is a popular commercial standard for wireless personal area networks and sensor network interfaces. The talk will focus on low-power receiver design using energy/bit as the design metric. The agenda of the talk will be:

  • Low power Timing Acquisition and Tracking Algorithms
  • Modeling and Simulation
  • Adaptive Receiver
  • Optimal Analog and Digital interface
  • Experiments on receiver boards
  • About the speaker: Satyam Dwivedi is a PhD student at the Indian Institute of Science, Bangalore. He works in the areas of physical layer of wireless communication, signal processing and circuit design. Satyam obtained his B.E. degree from MS University, Baroda, Gujarat, and M.E. degree from IISc in Electrical Communications. His master's thesis was related to Performance Improvements with Adaptive Modulation in CDMA and TDMA Systems. His PhD thesis is on Low-Power Architecture and Algorithms for Wireless Personal Area Networks (WPAN). He won the second place in a poster presentation on doctoral work competing with many PhD students from India at Techvista symposium organized by Microsoft Research. His research interests are in the areas of low-power system design, software radio, wireless personal area networks, etc.


    Frequency Compensation Techniques for Low-Dropout Voltage Regulators
    A talk Conducted by IEEE Circuits and Systems Society, Bangalore Chapter
    Speaker: Annajirao Garimella (New Mexico State University, Las Cruces NM, USA)
    Date: 4 May 2010
    Time: 3.00PM - 4.30PM      Download announcement (PDF 50 KB)
    Venue: CEDT, I.I.Sc Bangalore
    All are requested to attend. Please inform by mail to pvam@vsnl.net so that we know your interest. All CAS members are requested to attend to plan future activities.

    Abstract: When attempting to stabilize a low-dropout voltage regulator (LDO) or a multi-stage amplifier, the introduction of a Miller capacitor may create a feed-forward path and Right-Half-Plane (RHP) zero, jeopardizing the stability of the control loop. In addition to a nulling resistor, a voltage buffer or a current buffer can be placed in series with the Miller capacitor to obviate the feed-forward path and introduce a Left-Half-Plane (LHP) zero. A LHP zero, placed in its proper location, can cancel the effect of a pole and/or an RHP zero, boosting the phase margin, and improving large-signal stability.
    This talk explores some of the newest techniques in frequency compensation, after a solid introduction of the basics. Frequency compensation techniques using current buffers will be introduced. In addition to the popular common-gate (or cascade) transistor topology used as a positive current buffer, the recent technique of using current mirror as an inverting current buffer will be detailed. Simple design equations and design examples of frequency compensation using current buffers are detailed. The tutorial concludes by introducing an effective method of using a series resistor for accurate placement of current buffer LHP zeros.

    About the speaker: Annajirao Garimella is a Ph.D. Candidate in Electrical and Computer Engineering at New Mexico State University, Las Cruces, NM. He obtained M.S. in VLSI-CAD from Manipal University, Manipal, India, in 2002, a second M.S. in Electrical Engineering from New Mexico State University in 2009 and Bachelor of Engineering from University of Madras, India in 2000. He had pursued internship at Freescale Semiconductor Inc, Austin TX and at Texas Instruments, Dallas, TX. He is recipient of HENAAC (Hispanic Engineer National Achievement Award Corporation) AMD scholarship in 2005 and DaimlerChrysler Scholarship in 2006. His areas of interests include analog, mixed-signal IC design, power management IC design, SoC design and testing. He is a student member of IEEE and IEEE Circuits and Systems society.


    March
    Applications of Analog Electronics
    A faculty training program, jointly conducted by RNS Institute of Technology & The Board of Studies, VTU (Visvesvaraya Technological University). Sponsored by Texas Instruments India, In Co-operation with IEEE Circuits and Systems Bangalore Chapter & Cranes Software International Ltd, Bangalore
    Faculty: Prof. K. Radhakrishna Rao, TI India & Prof. Krishnamurthy Bhat, BEC Bagalkot
    Date: March 29 - 31, 2010
    Venue: RNS Institute of Technology, Bangalore      Download announcement (PDF 125 KB)
    The course is primarily intended for faculty from VTU. Faculty from other Universities will also be accommodated if there are vacancies. The course is relevant for faculty who teach Analog Electronics and related topics. Familiarity with SPICE simulation software will be necessary. Please refer to details on course outline and registration in the event announcement.

    A Century of Systematic Innovation: From Edison to Lafley
    PragaTI (TI India Technical University) announces a seminar in collaboration with IEEE-CAS Society, Bangalore Chapter and VLSI Society of India
    Speaker: Dr.Vinay Dabholkar
    Date: March 4, 2010
    Time: 3.30 - 4.30PM      Download announcement (PDF 25 KB)
    Venue: TI Bangalore Auditorium
    Registration is free for IEEE and VLSI Society of India members. Please register online through the link provided in the above PDF announcement before March 1, 2010.

    Abstract: Conventional wisdom says that innovation goes hand in hand with creativity and perhaps serendipity. Hence, many believe systematic and innovation don’t go together. Can we really innovate systematically? Let's explore this question through stories of two great innovation evangelists born 100 years apart. The first one is Thomas Edison who ran an invention factory successfully. The other one is A. G. Lafley, ex-CEO of Procter and Gamble who ran an innovation factory successfully. By comparing their approaches to innovation, we will see – What has changed? And what hasn’t? We will also see the difference between engineering-led vs marketing-led innovations.

    About the speaker: Dr. Vinay Dabholkar is an innovation catalyst and services innovation engines for living. For the past 3 years he has worked with 40 organizations in developing technical leadership and maturing innovation process. Currently, his focus is systematic innovation - a method invented by Thomas Edison and evolved over the past century. Prior to starting consulting business, Vinay worked with Sasken for 8 years and with Motorola for 2 years in engineering and marketing functions. Vinay has a B.Tech. in Computer Science from IIT Bombay and a PhD from SUNY Buffalo.


    January
    DLP® Technology: Extreme Versatility
    PragaTI (TI India Technical University) announces a seminar in collaboration with IEEE-CAS Society, Bangalore Chapter and IEEE Bangalore Section
    Speaker: Dr. Larry J. Hornbeck, Texas Instruments (Dallas)
    Date: 6th January 2010
    Time: 3.00 – 4.30 P.M.      Download announcement (PDF 134 KB)
    Venue: Auditorium, Texas Instruments India, Bagmane Techpark, C.V.Raman Nagar, Bangalore 560093
    There is no fee for the seminar and it is open to everyone. Due to limited seating, we will prioritize IEEE members over non-members. Please send an email to rahulkumar@ti.com before Dec 24, 2009 along with your IEEE membership (if any). Confirmation will be sent to you. Please arrive at least 15 min before the seminar begins to ensure seating. Limited parking is available in TI campus. Please carry your photo-id with you.

    Abstract: Microelectromechanical systems (MEMS) technologies are bringing value to many industrial and consumer products in the way of improved functionality and miniaturization. An example is the Digital Micromirror Device, a high-density array of up to two-million micromirrors with associated CMOS memory cells integrated together on a silicon chip. The synergistic combination of the DMD chip with optics and algorithms gives DLP® projection display technology a unique nature – the versatility to be leveraged over a broad range of applications. Today DLP technology enables the tiniest products (embedded in mobile phones), the brightest products (over 30,000 lumens) and virtually everything in between – all with leading world-class image quality. This seminar will provide an overview of the origins and workings of the technology and an understanding of traditional and new market applications. The seminar will focus more on technology than applications.

    About the speaker: After earning his Ph.D. in solid state physics from Case Western Reserve University in 1973, Larry J. Hornbeck joined the Central Research Laboratories of Texas Instruments in Dallas, Texas. Today, he is a TI Fellow working in the DLP® Products organization.
    Over the span of his career at TI, he has developed CCD image sensors, uncooled IR detectors, and reflective spatial light modulators (SLMs), the latter being his current field of endeavor. Hornbeck is best known as the inventor of the Digital Micromirror Device (DMD), an optical semiconductor with as many as two-million hinged, tiltable and individually controllable micromirrors integrated on a chip.
    After struggling for more than a decade to perfect analog micromirrors, Hornbeck was convinced that a radical new approach to the control of light was essential to overcoming the performance and image stability limitations inherent in his analog designs. Early in 1987 he had a major breakthrough with his invention of the DMD, the chip that would become the basis for the trademarked DLP technology from Texas Instruments. Hornbeck’s invention of rugged, fast, highly-reflective digital micromirrors integrated on a chip would in time create a revolution in projection imaging technology for home, office, entertainment, education and mobile applications. Who could have predicted in 1987 that twenty years later, film projectors, the last major imaging technology to yield to the semiconductor age, would be replaced in thousands of theaters around the world by digital micromirrors on a chip?
    The DMD manipulates light digitally, its tiny mirrors tilting thousands of times a second to create an image by directing pulses of light through a projection lens and onto a television, presentation, or movie theater screen. DLP® technology uses this highly versatile imaging technique to create a remarkable variety of display products that are virtually immune to image degradation. These range from the tiniest DLP pico-projectors embedded in cell phones, to a wide selection of DLP front-projectors and rear-projection HDTVs, to the largest projectors in the world, including TI’s DLP Cinema® projectors that light up nearly 11,000 theater screens globally, with more than 4,000 screens offering digital 3-D. At the 2008 Beijing Summer Olympic Games under the most adverse environmental conditions, sixty-three DLP Cinema projectors were combined to create the largest projected image in the history of visual technology, the 46ft (14m) high x 1,640 ft (500m) long overhead “raceway,” viewed live (or delayed) by an estimated 800 million people as they watched the Olympic Opening Ceremonies.
    Hornbeck holds a series of seminal patents that form the foundation for DMD technology. These include the first practical methods based on microelectromechanical systems (MEMS) concepts for manufacturing high-density arrays of micromirrors on an integrated circuit in a conventional wafer fab (1983); the Digital Micromirror Device, a MEMSbased array of fast, reflective, digital light switches monolithically integrated along with a digital address circuit on a silicon chip (1987); the surface lubrication technology for the DMD (1990); and others. As of 2007, he holds 33 U.S. patents in CCD, IR detector, and MEMS technology; others patents are pending.
    Hornbeck has received numerous national and international awards and honors, including an Emmy® Engineering Award from the Academy of Television Arts & Sciences “for digital micromirror technology.” In May 2009 he was honored by induction into the National Inventors Hall of Fame for his invention of the DMD. Together with the CRT and LCD, the DMD is only the third display device whose inventor has received National Inventors Hall of Fame status. He is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE), a Fellow of the International Society for Optical Engineering (SPIE), and an elected member of the National Academy of Engineering. Hornbeck and his wife, Laura, reside on a 32-acre property in the country near Van Alstyne, Texas, north of Dallas. They have two sons, Jason and David.
    National and International Awards and Honors:
    (1995) Germany’s Eduard Rhein Foundation Technology Award; (1997) England’s Rank Prize; (1998) Emmy® Engineering Award from the Academy of Television Arts & Sciences; (1999) Karl Ferdinand Braun Prize from the Society for Information Display; (2001) Electronic Imaging Honoree of the Year Award from the SPIE; (2002) The David Sarnoff Medal Award from the Society of Motion Picture and Television Engineers; (2002) elected Fellow SPIE; (2004) Small Times Magazine Best of Small Tech Lifetime Achievement Award; (2004) Daniel E. Noble Award from the Institute of Electrical & Electronic Engineers (IEEE); (2005) Progress Medal from the Photographic Society of America; (2006) elected Fellow IEEE; (2007) elected to the National Academy of Engineering; (2007) Progress Medal from the Royal Photographic Society; (2007) Prize for Industrial Applications of Physics from the American Institute of Physics; (2009) inducted into the National Inventors Hall of Fame for his invention of the DMD.


    Technology Trends and Options for High Performance CMOS FETs at the 15-nm Generation and Beyond
    PragaTI (TI India Technical University) announces a seminar in association with VLSI Society of India, IEEE-CAS Society, Bangalore Chapter and IEEE Bangalore Section
    Speaker: Prof. Dimitri A. Antoniadis, MIT Microsystems Technology Laboratories, Cambridge, Massachusetts
    Date: 5th January 2010
    Time: 4.00 – 5.00 P.M.      Download announcement (PDF 83 KB)
    Venue: Auditorium, Texas Instruments India, Bagmane Techpark, C.V.Raman Nagar, Bangalore 560093
    There is no fee for the seminar and it is open to everyone. Due to limited seating, we will prioritize IEEE members over non-members. Please send an email to rahulkumar@ti.com before Dec 24, 2009 along with your IEEE membership (if any). Confirmation will be sent to you. Please arrive at least 15 min before the seminar begins to ensure seating. Limited parking is available in TI campus. Please carry your photo-id with you.

    Abstract: The historical evolution of High Performance (HP) CMOS and the trends projected by the 2007 ITRS are critically examined. As in the ITRS, it is assumed that basic lithography and back-end scaling will continue well into the future according to their own roadmap and therefore only the aspects of FET dimensional and performance scaling are evaluated. Recent trends and research directions in performance boosters such as maximized strain in pure Si channels, new channel materials consisting of Ge, and Si/Ge and III-V heterostructures, and the required hi-k-metal-gate stack properties are surveyed and analyzed in context of device structures suitable for the 15-nm CMOS generation. Issues of source/drain resistance and gate capacitance as they affect FET performance are also discussed. Finally, tradeoffs between performance and power dissipation are also examined.

    About the speaker: Dimitri A. Antoniadis was born in Athens Greece. He received his B.S. in physics from the National University of Athens in 1970 and his Ph.D. in Electrical Engineering in 1976 from Stanford University. He joined MIT in 1978 where he holds the Ray and Maria Stata chair in Electrical Engineering. He is well known for seminal contributions to field-effect devices and to silicon process modeling. His present research focuses on the physics and technology of nano-scale devices in Si, Si/SiGe, and III-V materials for CMOS applications. Currently he is Director of the multi-university Focus Research Center for Materials Structures and Devices centered at MIT. He is Fellow of the IEEE, member of the National Academy of Engineering, and recipient of several professional awards.


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