IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Events - 2011
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December
Distinguished Lecture on Meeting the Signal Integrity Challenges in High-Speed Designs
Conducted In co-operation with IEEE-CAS Bangalore Chapter by PragaTI (TI India Technical University)
Speaker: Prof. Ramachandra Achar, Carleton University, Canada
Date: 14 December 2011
Time: 3.00 PM – 4.00 PM      Download announcement (PDF 92 KB)
Venue: TR-1, Texas Instruments, India, Bagmane Tech Park, CV Raman Nagar, Bangalore, 560093
There is no registration fee to attend the short course, and is open to a limited number of IEEE members. Registration is mandatory. Interested participants to send a mail to Harmanpreet Singh (harmanpreet@ti.com) before 5.00PM Dec 11, 2011 to register, and receive confirmation. Please carry photo identification, and approach the reception by 2.30 PM. Limited parking available for visitors

Abstract: The intense drive for signal integrity has been at the forefront of rapid and new development in CAD algorithms focused on VLSI designs. With the continually increasing demands for high signal speeds coupled with decreasing feature sizes, interconnect effects such as signal delay; distortion and crosstalk have become the dominant factors limiting the overall performance of high-speed systems. On the other hand, interconnect structures can be diverse and present at any of the hierarchical packaging levels including integrated circuits, printed circuit boards, multi-chip modules and backplanes. If not considered during the design stage, interconnect effects can cause failed designs. Since extra iterations in the design cycle are costly, accurate prediction of these effects is a necessity in high-speed designs. Although conventional CAD tools such as SPICE are used routinely by many engineers for analog simulation and general circuit analysis, these tools do not handle adequately the new emerging challenges of interconnect effects.
In this lecture, high-frequency issues and signal integrity in high-speed VLSI designs will be discussed. Fundamentals and advances in signal integrity modeling/simulation/design will be presented. Various levels of interconnect modeling will be considered and the applications cover wide spectrum of on-chip, multichip, packages, printed circuit boards, backplanes and connectors.

Prof. Ramachandra AcharAbout the Speaker: Prof. Achar is an active researcher contributing to the advancement of computer-aided design tools and methodologies for analysis of high-frequency circuits and systems. He has published over 150 peer-reviewed articles in international journals/conferences, six multimedia books on signal integrity and five chapters in different books.
Prof Achar received the B. Eng. degree in electronics engineering from Bangalore University, India in 1990, M. Eng. degree in micro-electronics from Birla Institute of Technology and Science, Pilani, India in 1992 and the Ph.D. degree from Carleton University in 1998. He currently serves as a professor in the department of Electronics Engineering at Carleton University, Ottawa, Canada.
Prof. Achar received several prestigious awards, including Carleton university research achievement awards (2010 & 2004), NSERC (Natural Science and Engineering Research Council) doctoral medal (2000), University Medal for the outstanding doctoral work (1998), Strategic Microelectronics Corporation (SMC) Award (1997) and Canadian Microelectronics Corporation (CMC) Award (1996). He was also a co-recipient of the IEEE advanced packaging best transactions paper award (2007). Also several of his students have won numerous best student paper awards in international forums. Many of his contributions have already been adopted by leading industries, such as IBM, ADI and CST etc.
Dr. Achar currently is a Distinguished Lecturer (DLP) of the IEEE Circuits and Systems Society (CASS) and is the general co-chair of IEEE international conference on Electrical Performance of Electronic Packages & Systems (EPEPS). He also currently serves on the executive/steering/technical-program committees of several leading conferences, such as EPEPS, EDAPS, SPI, ASP-DAC etc. He is a member of the Canadian standards committee on nanotechnology, chair of the joint chapters of CAS/EDS/SSC societies of the IEEE Ottawa Section, and is a consultant for several leading industries focused on high-frequency circuits, systems and tools. Dr. Achar is a practicing professional engineer of Ontario. He is a frequently invited speaker, consultant, reviewer and organizer on signal integrity and high-speed issues. For more details about Dr. Achar, his Research Activities/Contributions and Publications, Please visit: http://web.doe.carleton.ca/~achar/


November
A two-day Conference on Architecture, Programming & Applications of Stellaris (ARM Cortex-M3) Microcontroller
Jointly conducted by Texas Instruments University Program (UniTI) and IEEE CAS Bangalore Chapter
Speakers: Please refer the announcement
Date: 19-20 November 2011
Time: 8.30 AM – 7.00 PM      Download announcement (PDF 85 KB)
Venue: Texas Instruments, India, Bagmane Tech Park, CV Raman Nagar, Bangalore, 560093
There is a participation fee of Rs. 1000/- for teachers and Rs 500/- for students. The fee will cover the cost of registration materials, participation certificate, lunch and refreshments on both days. Please arrive by 8.00 AM, and carry photo identification. Limited parking available for visitors.
Pre-requisites: Participants must have a good knowledge of C programming and must have taken a course on Microprocessor/Microcontroller. A limited number of seats are available, please refer the announcement for registration details.

Abstract: Texas Instruments offers a broad portfolio of embedded processor platforms based on ARM processor cores which are known for low-power and high performance. The Stellaris family of microcontrollers are based on ARM Cortex-M3 processor. Stellaris microcontrollers work at clock speeds up to 100 MHz and are optimized for low power. They support a number of peripheral interfaces, such as Ethernet and USB and support on-chip ADC. Their applications include industrial automation, motor control, robotics, general-purpose computing, and many others. This conference will provide hands-on exposure to TI’s Stellaris Microcontroller development platforms. Other than talks on Stellaris architecture, programming, and applications, the conference will also feature two hands-on workshops:

  • Workshop I on "Robotics Experiments using Stellaris EVALBOT" will be based on the robotics development kit LM3S9B92 from Texas Instruments OR
  • Workshop II on "Applications of Ethernet Connectivity and CAN Interface in Stellaris" based on Stellaris microcontroller – will be based on the LM3S8962 evaluation board with CAN + Ethernet

  • This event is intended for teachers and undergraduate & postgraduate engineering students from Indian institutions. Prior registration is mandatory (please see registration instructions). The participants will be able to attend any one of the two workshops.


    September
    Topics in Analog Power Management
    In collaboration with IEEE Circuits and Systems Society, Bangalore Chapter, PragaTI (TI India Technical University) announces a Seminar
    Speaker: Sujan Manohar (University of Texas, Dallas)
    Date: 8 September 2011 (Note: Date moved from 18 May 2011)
    Time: 3.00 AM – 4.00 PM      Download announcement (PDF 65 KB)
    Venue: Jack Kilby Auditorium, Texas Instruments, India, Bagmane Tech Park, CV Raman Nagar, Bangalore, 560093
    There is no registration fee to attend the seminar, and is open to a limited number of interested participants who are IEEE members. To register, please send a mail to Saurabh Rathor (saurabh.rathor@ti.com) no later than 5.00PM - Sep 5, 2011 for a confirmation. Please arrive by 2.30 PM, and carry photo identification. Limited parking available for visitors.

    Abstract: This talk will cover the topics on Analog Power Management Circuits, such as CMOS Charge pumps, NEM device charge pumps for higher efficiency as opposed to CMOS, and higher performance NEM flip-flops using selective charge boosting technique.
    Target Audience: This course is open to everyone.

    About the Speaker: Sujan Manohar is a doctoral student in the Department of Electrical and Computer Engineering at University of Texas, Dallas. He was awarded the Texas Analog centre of Excellence doctoral fellowship sponsored by TI/SRC. His research interest is in the area of analog and power management circuit design, with specialization in analog power management circuits. Sujan was a senior design engineer with Texas Instruments, India during 2004 -- 2008. He has a B.E. degree in Electronics and Communication Engineering from RVCE, Bangalore and MS degree from University of Texas, Dallas. He has published several papers in IEEE conferences and journals and has delivered several seminars in the area of analog and power management circuit design. He holds 10 US patents in the area of circuit design of which few are in processing at USPTO.


    July
    DC Nano-grid: Concept to Realization
    In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, PragaTI (TI India Technical University) announces a Seminar
    Presenter: Dr. Shantanu K Mishra (IIT Kanpur)
    Date: July 19, 2011
    Time: 3:00 PM to 4:00 PM
    Venue: Jack Kilby Auditorium, Texas Instruments India; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
    Keywords: Nano-Grids, Energy, Power Management, Power Converters
    There is no fees to attend, but registration by intimation is mandatory. Pleae inform Saurabh Rathor (saurabh.rathor@ti.com) before 6.30pm on Monday (18-7-2011). Your participation will be confirmed by e-mail. Please arrive 15 minutes before the seminar. Limited parking is available. Please carry your photo-id with you and collect a badge at the reception. Return the badge when you leave.

    Abstract: In this seminar, the concept of DC nano-grid will be introduced and its architectural details will be presented. The overall system can be either grid connected or islanded.
    Storage is an important part of a nanogrid. The role of power management is paramount to the realization of these systems. Various converters suitable for the DC nanogrid will be discussed.


    May
    Zigbee Development on TI Platform
    In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, and VLSI Society of India, PragaTI (TI India Technical University) announces a Short course
    Instructor: Adithya Gajulapally (Texas Instruments, India)
    Date: 20 May 2011 (Note: Date moved from 18 May 2011)
    Time: 10.00 AM – 5.00 PM      Download announcement (PDF 76 KB)
    Venue: TR-1, Texas Instruments India; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
    There is no registration fee to attend the seminar, and is open to a limited number of interested participants who are members of IEEE/VSI. To register, please send a mail to Karan Tiwari (karan.tiwari@ti.com) no later than 5.00PM - May 16, 2011. Please arrive by 9.30 AM, and carry photo identification. Limited parking available for visitors.

    Objective: To provide quick introduction to Zigbee and TI Zigbee products. 1) Overview of Zigbee with more focus on top layers 2) TI products and Zigbee stack 3) Application development on TI Zigbee products (Hands on).
    Target Audience: The course is most useful for beginners who are interested in getting to know Zigbee protocol with some hands-on practice. It is expected that the participants have an exposure to concepts of computer networking. Background in C programming is mandatory.

    About the instructor: Adithya Gajulapally obtained a B.Tech in Computer Science from ICFAI University (Tripura) in 2010. He joined TI Bangalore as a consultant with the Focused End Equipment group, and works on the integration of Zigbee into Android.


    An Overview of ARM Processor Architectures and Technologies
    In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, and VLSI Society of India, PragaTI (TI India Technical University) announces a Seminar
    Speaker: William Hohl (ARM Embedded Technologies)
    Date: 18 May 2011
    Time: 11.00 AM – 12.00 PM      Download announcement (PDF 69 KB)
    Venue: Texas Instruments India Auditorium; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
    There is no registration fee to attend the seminar, and is open to a limited number of interested participants who are members of IEEE/VSI. To register, please send a mail to Karan Tiwari (karan.tiwari@ti.com) no later than 5.00PM - May 16, 2011. Please arrive by 10.30 AM, and carry photo identification. Limited parking available for visitors.

    Objective: This 1-hour lecture outlines the ARM architectures and technologies. Specifically, we will examine the ARM architecture, including the programmer’s model, instruction sets, pipelines, AMBA, and development tools and resources that are available to students. This presentation is designed to answer questions at the most technical level.
    Target Audience: The course is most useful to developers and application engineers who work on platforms based on ARM processor cores.

    About the speaker: William Hohl has been with ARM for 14 years, first as a principal design engineer on the ARM10 design team, then as head of U.S. support operations, and finally as Worldwide University Relations Manager. Previously, he worked at Motorola, helping to design the first generation of ColdFire microprocessors, and with Texas Instruments as an Applications Engineer in the DSP and ASIC divisions. He is a Senior Member of IEEE and the author of the bestselling book ARM Assembly Language - Fundamentals and Techniques. He holds an MSEE and BSEE from Texas A&M University, as well as 6 US patents.


    April
    Next-Generation Ultra-Low-Power System Design
    In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, and VLSI Society of India, PragaTI (TI India Technical University) announces a Seminar
    Speaker: Anantha P. Chandrakasan (Joseph F. and Nancy P. Keithley Professor of Electrical EngineeringDirector, MIT Microsystems Technology Laboratories)
    Date: 28 April 2011
    Time: 11.00 AM – 12.00 PM      Download announcement (PDF 42 KB)
    Venue: TR-1, Texas Instruments India; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
    There is no registration fee to attend the seminar, and is open to a limited number of interested participants who are members of IEEE/VSI. To register, please send a mail to Karan Tiwari (karan.tiwari@ti.com) no later than 5.00PM - April 26, 2011. Please arrive by 10.30 AM, and carry photo identification. Limited parking available for visitors.

    Abstract: Next-generation handheld devices and wireless sensors for health and environmental monitoring, will require dramatic reduction in energy consumption. The ultimate goal is to power these devices using energy-harvesting techniques such as vibration-to-electric conversion, or through body heat. A system-level approach must be used to optimize such devices. Relevant considerations include ultra-low-voltage digital circuit operation, application-specific digital and mixed-signal architectures, extreme parallelism, computation vs. communication trade-off, and integrated energy-processing circuits. The use of analog-assisted digital circuits (such as embedded switched-capacitor power management, and offset compensation in sense amplifiers) will be critical in dealing with device variability and low-voltage operation. Efficient energy-processing circuits (for generation, buffering, and conversion) is critical in many applications. Several system examples will be shown, covering portable biomedical and multimedia devices.

    About the speaker: Anantha P. Chandrakasan received the B.S, M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 1989, 1990, and 1994 respectively. Since September 1994, he has been with the Massachusetts Institute of Technology, Cambridge, where he is currently the Joseph F. and Nancy P. Keithley Professor of Electrical Engineering.
    He has been the co-recipient of several awards including the 1993 IEEE Communications Society Best Tutorial Paper Award, the IEEE Electron Devices Society 1997 Paul Rappaport Award for the Best Paper in an EDS publication during 1997, the 1999 DAC Design Contest Award, the 2004 DAC/ISSCC Student-Design-Contest Award, the 2007 IEEE ISSCC Beatrice Winner Award for Editorial Excellence, and the IEEE ISSCC Jack Kilby Award for Outstanding Student Paper (2007, 2008, 2009). He received the 2009 Semiconductor Industry Association (SIA) University Researcher Award.
    His research interests include low-power digital integrated-circuit design, wireless microsensors, ultra-wideband radios, and emerging technologies. He is a co-author of Low Power Digital CMOS Design (Kluwer Academic Publishers, 1995), Digital Integrated Circuits (Pearson Prentice-Hall, 2003, 2nd edition), and Sub-threshold Design for Ultra-Low Power Systems (Springer 2006). He is also a co-editor of Low Power CMOS Design (IEEE Press, 1998), Design of High-Performance Microprocessor Circuits (IEEE Press, 2000), and Leakage in Nanometer CMOS Technologies (Springer, 2005).
    He has served as the Technical Program Co-Chair for the 1997 International Symposium on Low-Power Electronics and Design (ISLPED), 1998 VLSI Design, and the 1998 IEEE Workshop on Signal-Processing Systems. He was the Signal_Processing Sub-Committee Chair for ISSCC 1999-2001, the Program Vice-Chair for ISSCC 2002, the Program Chair for ISSCC 2003, the Technology-Directions Sub-Committee Chair for ISSCC 2004-2009, and the Conference Chair for ISSCC 2010 and 2011. He was an Associate Editor for the IEEE Journal of Solid-State Circuits from 1998 to 2001. He served on SSCS AdCom from 2000 to 2007; and he was the Meetings Committee Chair from 2004 to 2007. He is the Director of the MIT Microystems Technology Laboratories (MTL), which has over 700 users.


    March
    yukTI – A smart & economical domotic solution
    In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, and VLSI Society of India, PragaTI (TI India Technical University) announces a Seminar
    Speakers: Amogh N, Arun Mohan Kumar, Joseph John and Lee Aby Zachariah (Texas Instruments, India)
    Date: March 23, 2011
    Time: 3.00 PM - 4.00 PM      Download announcement (PDF 35 KB)
    Venue: TR-1, Texas Instruments India; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
    There is no registration fee to attend the seminar, and is open to a limited number of interested participants who are members of IEEE/VSI. Please send a mail to Karan Tiwari (karan.tiwari@ti.com) to receive confirmation. Please arrive by 2.30 PM, and carry photo identification. Limited parking available for visitors.

    Abstract: Home Automation is a booming market sector, which has lot of potential for innovation and exploration. Currently all electrical/electronic appliances need to be controlled individually and require physical presence near the device to control it. Existing home automation solutions either use one remote per few devices or are costly. User finally ends up with different remotes to operate several devices. Even if a new device is introduced by the same company, it cannot be controlled with the existing remote.
    As the number of controllable appliances in a home rises, the ability to control these with a handheld remote becomes a useful and desirable feature. Creating a smart home has been a dream for many years but it’s still not prevalent because of the expensive modules and not well-defined ease of use.


    February
    Op-Amp Noise Calculation and Measurement
    In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, and VLSI Society of India, PragaTI (TI India Technical University) announces a Seminar
    Date: February 3, 2011
    Time: 4.00 PM - 5.30 PM      Download announcement (PDF 80 KB)
    Venue: TR-1, Texas Instruments India; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
    There is no registration fee to attend the seminar, and is open to a limited number of interested participants who are members of IEEE/VSI. Online registration is mandatory. Participants must register online no later than January 30, 2011. Your participation will be confirmed. Please arrive by 3.30 PM, and carry photo identification. Limited parking available for visitors.

    Abstract: This presentation covers calculation, simulation, and measurement of intrinsic noise. Intrinsic noise is noise generated by resistors, op-amps, and other active devices in the circuit. The presentation does not cover extrinsic noise (e.g. RFI, and EMI pick-up). The presentation covers specific real world examples, where the peak-to-peak output noise is predicted and measured.

    About the speaker: Arthur Kay is the linear applications manager at Texas Instruments. He specializes in the support of sensor signal conditioning devices, and industrial applications. Art has also focused on the topic of noise and has published a series of articles on noise. Before working in applications engineering, he was a semiconductor test engineer for Burr-Brown and Northrop Grumman Corp. Art graduated from Georgia Institute of Technology with an MSEE.


    Fundamentals of the ECG Signal Chain
    In cooperation with IEEE Circuits and Systems Society, Bangalore Chapter, and VLSI Society of India, PragaTI (TI India Technical University) announces a Seminar
    Date: February 2, 2011
    Time: 4.00 PM - 5.00 PM      Download announcement (PDF 38 KB)
    Venue: TR-1, Texas Instruments India; Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
    There is no registration fee to attend the seminar, and is open to a limited number of interested participants who are members of IEEE/VSI. Online registration is mandatory. Participants must register online no later than January 30, 2011. Your participation will be confirmed. Please arrive by 3.30 PM, and carry photo identification. Limited parking available for visitors.

    Abstract: This presentation will provide a background on the biology, sensor interface, and terminology of ECG as well as detail some of the discrete electrical design considerations in designing the analog front end (AFE), input filtering and protection, discrete gain and band pass filtering, and A/D conversion in an ECG data acquisition system. Also covered within the presentation will be ECG functions such as PACE Detection, Lead Off Detection, RL Drive bias, Wilson Central bias, and the methods used to obtain of the leads in a complete 3-12 lead system. This presentation will conclude with an overview of the ADS129x (4, 6, and 8 channel versions), an 8 channel, 24 bit, low noise, simultaneous sampling ECG AFE with all of the discrete ECG functions included in one chip.

    About the speaker: Matthew Hann is the manager for Precision Analog Products in the High Performance Analog business unit at Texas Instruments. Matt's areas of product expertise include temperature sensors, difference amplifiers, instrumentation amplifiers, programmable gain amplifiers, power amplifiers, and the ADS129x/119x line of ECG AFE devices. Through his role as an applications engineer Matt has developed a focused expertise on the design of analog front ends for medical applications such as ECG, EEG, EMG, Blood Glucose Monitoring, and Pulse Oximetry as well as a variety of sensor signal conditioning and temperature sensing applications.

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