IEEE - CAS Bangalore Chapter, India CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems
Event Reports - 2005
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VLSI Physical Design Automation Workshop - Introduction to VLSI CAD
Dec 22-24, 2005, Bangalore
Report by C.P.Ravikumar
VLSI Society of India organized a three-day Course on VLSI Physical Design Automation - Introduction to VLSI CAD during Dec 22-24, 2005. The course was held in cooperation with IEEE Solid State Circuits Society and IEEE Circuits and Systems Society, Bangalore Chapter. Prof..Dinesh Bhatia, University of Texas at Dallas, conducted the course. The course was held at Hotel Atria and was attended by over 32 participants.
Physical Design is one of the most challenging tasks in the design cycle of a VLSI chip. Design automation related issues for the current state of the art was the main theme of the course. Data structures and algorithms related to design automation were introduced to provide insight into design of CAD tools.
The course aimed at providing an understanding and relationships between design automation algorithms and various constraints posed by VLSI fabrication and design technology. Critical performance related parameters and their importance in design automation tools were introduced.
The participants gave enthusiastic feedback to the course.
VLSI Signal Integrity Workshop
December 16 - 17, 2005, Bangalore
Report by C.P.Ravikumar
VSI organized a two-day Workshop on VLSI Signal Integrity at Hotel Atria, Bangalore during December 16 - 17, 2005. About 50 participants attended the workshop. The event was held in cooperation with IEEE Circuits and Systems Society, Bangalore Chapter.
With VLSI technology scaling continuously, designers have to deal with problems of signal integrity. Capacitive cross coupling between adjacent wires can lead to glitches and/or delay variations. Simultaneous switching of signals in the circuit can lead to power integrity problems. Precautions are necessary to ensure that signal integrity problems do not lead to failures during circuit operation. Over the past decade, EDA tools and design flows have evolved to deal with signal integrity problems. Addressing these issues, thie workshop dealt with various aspects of signal integrity to provide both a tutorial overview as well as an industrial perspective of the problem.
On Day 1, the workshop began with Opening Remarks by Dr Ram Achar, Carleton University, Canada. This was followed by four technical sessions. Session I began with a talk entitled “Introduction to Signal Integrity Problems in DSM - An Industry Perspective” by Dr. Ashok Balivada, Analog Devices, India. Session II featured a talk by C.P. Ravikumar on “Signal Integrity Issues in Design For Test .” In Session III, Dr Ram Achar covered a Review of Circuit Simulation. In Session IV, Arvind of Texas Instruments India gave a talk on “Static Timing Analysis with Signal Integrity”.
Day 2 included four technical sessions. During Session V, Dr. Ram Achar spoke on Transmission Line Interconnects, SPICE Macromodels and comparative study of industry tools for signal integrity. Session VI included a talk by Dr. Shabbir Batterywala, Synopsys, India on the topic of Circuit Extraction. In Session VII, Dr Ram Achar delivered a talk on Measurements, Multiport Parameters and scattering parameter based macromodels for
circuit analysis. The workshop ended with a Panel Discussion on “Signal integrity - Challenges Ahead” which was coordinated by Dr Ram Achar. The panelists included the speakers in the workshop. The course received enthusiastic response from the participants.
Workshop on Verification Methodologies
Nov 25, 2005, Hotel Atria, Bangalore
A Report by C.P.Ravikumar
Design Verification is one of the most time-consuming of all the steps in the design flow. Many new methodologies are emerging to improve the cycle time of design verification. In order to explore new developments in the area of design verification, VSI organized a one-day workshop on design verification methodologies on Nov 25, 2005 at Hotel Atria. It was attended by about 60 participants, mostly from the industry. A total of six speakers from Indian VLSI industry shared their experiences in different areas of verification.
P Mahesha of Wipro Technologies, Bangalore, delivered a talk on “Getting to 100% Functional Coverage - Challenges for the Verification Engineer.” He compared verification engineers to surgeons who hold the lives of the patients when they operate on them. A patient can die due to a doctor’s mistake - likewise, a chip can turn out to be buggy due to incomplete functional verification. He quoted statistics that only 65% of the designs that tare taped out see first-pass silicon success. He went into aspects of test planning and skill sets of verification engineers that can guarantee 100% functional coverage.
The second talk provided an overview of System Verilog as a hardware description/verification language. The talk was given jointly by Badri Gopalan (Aegia) and S. Venkataraman (Synopsys). Badri Gopalan pointed out that Verilog is today where schematic capture was about 15 years ago - there is a need to raise the level of abstraction for enhancing productivity. System Verilog is a single language for design and verification. The speakers went into a number of nuances in System Verilog which give the language significant power as a verification language. The speakers described how to write testbenches and assertions in SV.
Venkatesh Swaminathan of Intel delivered a talk on “An Environment for executing full chip pre-silicon environment on Post-silicon,” where he described a solution that Intel has adopted in reusing the pre-silicon verification environment on Post-silicon as well. This adds significant value since it can reduce cycle time and costs.
Vinaya Singh of Cadence delivered a talk on “Is Formal ABV usable for real verification?” where he explored various facets of formal assertion-based verification. He pointed out that a number of users of ABV are beginning to see significant success on large blocks. However, the technique is still not ready for full system-on-chip verification.
Sundaresan Kumbhakonam (Sun) from Broadcom made a case for hardware verification languages (HVL) in his presentation entitled. “How HVL based environments are beneficial over Verilog/C based environments.” He gave strong arguments in favor of using HVL environments such as Vera or SPECMAN instead of the traditional Verilog or C.
Venkatesh Natarajan of Texas Instruments gave a tutorial on the use of emulators for hardware verification in his talk entitled “Emulation-based Verification”. He brought out the need for emulation (as opposed to simulation) and explained the scenarios where emulation is the preferred solution. He also discussed the limitations of emulation-based verification.
The workshop was sponsored and organized by VSI in cooperation with IEEE Circuits and Systems Society and the Design Verification Forum. This is the first public event for the Design Verification Forum, which presently consists of a small number of verification enthusiasts from the industry. Y.S. Harish of Texas Instruments, who is a spokesman for the forum, described the goals of the forum and invited participants to take part in the activities of the forum. The website of the forum is accessible from .
The workshop was highly interactive and provided a forum for learning from one another. The feedback from the participants for the workshop has been very positive.
VLSI Design and Test Symposium, VDAT 2005
August 10-13, 2005
Wipro Tecnologies, Electronics City, Bangalore
A Report by C.P.Ravikumar
VDAT 2005 was held in Bangalore at Wipro Learning Center during Aug 10-13, 2005. From 2005, VDAT has acquired the status of a Symposium. The Symposium featured 2 full-day tutorials on August 10, one full day dedicated to VLSI Education in India, and 2 days of Symposium featuring keynote talks, technical paper presentations, invited talks, embedded tutorials, and a panel discussion. The complete technical program is available from the website - http://vlsi-india.org/
The symposium was inaugurated by Prof. Balaveera Reddy (the Vice Chanellor of VTU), Dr Bobby Mitra (President, VSI), Dr. Surendra Pal (Chairman, IEEE Bangalore Chapter), A. Vasudevan (Wipro Technologies) and Prof. Vishwani Agrawal (Auburn University). Prof. Reddy spoke about industry-academia interaction and announced the MoU between VTU, ISA, and VSI. Dr Surendra Pal spoke about the importance of events such as VDAT conducted by professional bodies such as IEEE and VSI. A. Vasudevan expressed his happiness about hosting VDAT at Wipro Technologies and welcomed everyone to the campus. Prof. Vishwani Agrawal released the periodical of the VSI (VSI VISION). Dr Bobby Mitra gave a keynote talk entitled "High Tech Education in India," and spoke about the growing needs of the Indian semiconductor industry and how to bridge the gap.
As part of the VLSI Education Day, the following discussions were held.
Taking student projects to silicon - the panelists were Dr Debashis Dutta of Ministry of Information and Communication Technology who announced the beginning of SMDP-II program, Dr. D.N. Singh of SCL, Chandigarah, who announced the details of the "India Chip" Program, Dr. Dinesh Sharma of IIT Bombay who emphasized the need for "silicon exposure" in M.Tech curricula, and Dr. Satya Gupta who said ISA will announce a program that will help Indian Universitites to take student projects to silicon.
Student Projects in Front-End Design - the panelists were Taher Abbasi, S. Karthik, V. Kamakoti, and M. Balakrishnan.
Student Projects in Physical Design - the panelists were Anand Anandkumar, Navakanta Bhat, G.S. Visweswaran, Uma Mahesh, and Shabbit Batterywala.
Student Projects in Test and Verification - panelists included Jayanata Lahiri, Prof Vishwani Agrawal, Dr R. Parekhji, Dr Subir Roy, and Dr S. Venkat
The role of industry in VLSI Education - panelists included C.P. Ravikumar, Dr P.P. Das, Dr H.V. Ananda, and Prof. K. Jayaram.
All the discussions in the VLSI Education Day were well attended and generated lively debate with strong participation from the audience.
The keynote speakers at the symposium were - Dr Tom Williams (Synopsys), Dr. Kaushik Roy (Purdue University), Dr. Sumeet Agarawal (Intel), and Mr. Ramesh Emani (Wipro Technologies). The invited speakers included Dr Nilanjan Mukherjee (Mentor Graphics), Dr. Susmita Sur-Kolay (ISI Calcutta), and Dr. Ashok Balivada (Analog Devices).
The symposium featured about 45 technical paper presentations that represented various diverse areas and came from both academia and industry. A brainstorming session on future events of the VSI was held as part of the symposium. A panel discussion on "What is the need of the hour for Indian VLSI Industry - Execution or Innovation?" was held. The panelists who supported "Execution" included Dr Mahesh Mehendale of Texas Instruments and Mr A. Vasudevan of Wipro. Mr Rajendra Khare (Broadcom) and Mr. Rajat Gupta (Beecem Communications) spoke in favor of "Innovation." The debate generated a lot of enthusiasm and elicited several questions from the audience.
The symposium was sponsored by VSI and was held in cooperation with IEEE TTTC, IEEE CAS Society, Bangalore Chapter, and IEEE EDS/SSCS society, Bangalore Chapter. The corporate sponsors for VDAT were Wipro Technologies, Texas Instruments, and Intel.
About 300 participants took part in the Symposium. About 100 fellowships were granted to students and faculty to enable them to attend VDAT. The feedback from the participants was enthusiastic.
VSI takes this opportunity to thank everyone who contributed to the success of VDAT 2005. Please send suggestions on improving VDAT to firstname.lastname@example.org. The announcement of VDAT 2006 will be made by November 2005.
Panel discussion: "Students Projects in Verification and Test - Ideas and Execution challenges"
Panelists: Dr. Viswani Agrawal & Dr. Rubin Parekhji spoke on Test while Swami Venkat & Subir Roy spoke on Verification.
Date: 11th August
Dr. Viswani Agrawal said there could be lot of work on ATPG algorithm, new fault method, new design for testability. He mentioned there are three categories of projects
Reserach oriented --mainly academia works on these.
Engineering practises -- Indutry does it
Test Economics -- Mangaement oriented. Mostly concentrated on how much customer can pay for detailed test coverage.
He is of the opinion that students’ talent should be matched with these three types of project.
Swami Venkat mentioned in design cycle 70% is verification & 30% design.
Design complexity increased so verification became an issue. System verification simulation is very important for codes running from 10K to 150 lines. Much faster verification. Assertions -> capture the protocols. Simulation test benches can be written with System Verilog. As students project people can write assertions for protocols like PCI-X, AMBA, USB 2.0
Resources required are System Verilog tool.
Rubin Parekhji said domain knowledge for doing students project in testing are:
Defects, Faults, Tests, design for test.
Any free tools can be used for ATPG.
Subir Roy stated lot of students work can be generated on Formal verification.
Some of the student projects can be carried out on Sun Pico Java, Texas -97 benchmark designs. He also emphasized to have a open environment with Unix/GNu etc.
Some of the Open tools, which the students can use, are SMV, NuSMV, and VIS3.1. Some of the commercial tools for verification are IFV, Periscope, Magellan, and Jasper.
Some students asked if there is any site where they can learn the testability aspects of analog circuits like PLL, etc. The panelists were not aware of such a website.
VLSI Society of India held a 4-day Intensive Course on Design for Testability - Theory and Practice, during July 27-30, 2005 at Bangalore. Dr.Vishwani D. Agrawal and Prof.Adit D. Singh (Auburn University) conducted the course as Instructors. About 60 participants, from the industry, faculty and notably the students attended the event.
The event was co-sponsored by IEEE Circuits and Systems Society, Bangalore chapter, IEEE - CS - Test Technology Technical Council (TTTC) and Tessolve as the corporate sponsor.
Dr.Vishwani D. Agrawal and Prof.Adit D. Singh
The course covered:
The exponential nature of the testing problem
Test generation for combinational circuits
PODEM, FAN and learning based ATPG
Test generation algorithms for sequential circuits
Scan and partial scan design
Functional testing of microprocessor/controllers
Design for testability
Built in self-test (BIST)
Test compression techniques for test data volume reduction
Boundary scan and the IEEE 1149 testability standard
Custom LSI Design Workshop
Manipal, June 6-18, 2005
A Report by S. Mahant Shetti, KARMIC (Karnataka Microelectronics), Manipal email@example.com
VSI and KARMIC jointly sponsored a workshop on Custom LSI Design for faculty and students from Engineering Colleges. The aim of the workshop was to select a limited number of faculty and students from the same college and train them in the use of public domain tools for VLSI CAD. In particular, the focus of the workshop was to use MAGIC and SPICE for custom-designing reasonably large circuits. The aim was also to encourage students and faculty to come up with good design decisions. Judicious algorithmic approximations can provide great advantages in chip area, speed and power. Numerous approximate solutions exist for a problem compared to the optimum solution; engineering judgment is vital in selecting the appropriate solution. The focus of the workshop was to explore “VLSI friendly” algorithmic approximations and realize them in a design.
Forty selected participants, ranging from second semester students to a head of the Electronics and Communications department in an Engineering college attended the workshop. The participants were divided into two groups to carry out two separate projects. The first group included 24 persons and the goal of this group was to design a chip for Euclidean distance calculation. Although the problem looks deceptively simple, the key was to come up with approximations to the square root function that yield low-area designs. The second group of 16 members considered the problem of generating two PWM current waveforms, where one is proportional to sine and the other cosine of a given input. Once again, approximation techniques were necessary to generate the sine and cosine functions. The emphasis of the first project was to consider speed/area tradeoff; in the second project, minimizing area was the primary goal. Leaf cells were generated for the data path in each of the projects, Bit-slice routing was done and top-level routing was completed. Only public domain tools, Open Office Calc, MAGIC and SPICE were used. The participants were also trained on installation of these tools so that they can establish a similar environment in their parent institutions.
The entire workshop was primarily hands-on, and lectures were held on demand from the participants. The concluding function had expert lectures by Dr Navakant Bhat and Dr. Narasimha Bhat, chaired by Dr. S J Bhat. Project groups made their presentations in the afternoon of the concluding day. The coastal city of Manipal, otherwise prone to constant rain, surprisingly remained dry, adding to the success of the workshop. The schedule for the projects was hectic and the demanded total involvement from the participans. Between the two projects, one made better progress compared to the other. The participants were urged to take up improvements to their design at their own parent institutions. The projects will also be presented at the VLSI Design and Test Symposium, Bangalore.
Here are some statistics on one of the projects to indicate the level of effort needed to do a reasonable job*:
Estimate of average time spent by about 50% of the team18hrs/day Estimate of average time spent by remaining members4 hrs/day Number of transistors in the design3500 Number of Unique Transistors300 Area of the design (0.35um TSMC CMOS technology)0.3mm^2 Size of SPICE file1 MB Size of Mag (Magic internal format) file250KB
*Some members of the group are continuing the work since they are not happy with the results. It will probably take another two learning cycles to get proper transistor sizing done and more detailed simulations completed.
Note from the VLSI Society of India: We thank the tireless efforts from Dr. Mahaht Shetti and his colleagues at KARMIC for making this unique experiment in VLSI Education possible. KARMIC also generously hosted the participants in Manipal during the course of the workshop.
Low Power Design Techniques
Report by C.P.Ravikumar
VSI held a two-day workshop on Low power Design Techniques during February 25-26, 2005. The workshop was conducted in co-operation with IEEE Circuits and Systems Society (Bangalore Chapter), and IEEE Electron Devices and Solid State Circuits Society. The venue was the Golden Jubilee Hall, ECE Dept, IISc - Bangalore. The workshop featured a wide range of reputed speakers. Dr Surendra Pal, Chairman of the IEEE Bangalore Section. Dr Pal expressed happiness over such an event being organized in Bangalore.
The workshops were attended by 122 participants, consisting of research scholars, faculty, industry professionals, and students. Several invitees were also present at the workshop, such as Dr P.V. Ananda Mohan (President, IEEE CAS Society, Bangalore Chapter), Dr P.R. Suresh (President, IEEE EDS Society, Bangalore Chapter), Dr Raghunathan Kuppuswamy (President, CPMT Bangalore Chapter), and Prof. Amara Amara of ISEP France.
Dr. P.V.Ananda Mohan inagurating the workshop
The feedback for the workshop was excellent and the participants expressed the need for more such workshops. The informal environment of the workshop and the speakers’ involvement with the audience was highly appreciated. The proceedings of the workshop in CD format is available from VSI.
The workshop had the following topics: Day-1
Session-1: System-level Power Optimization by Dr. Bharadwaj Amruthur, Assistant Professor, Department of ECE, IISc., Bangalore.
Session-2: Ensuring Power Integrity: Analysis and Closure Challenges by Kalpesh Shah, Texas Instruments, India
Session-3: Novel Device Architectures and Processes for the 65 nm CMOS Technology Node and Beyond by Dr. V. Ramgopal Rao, IIT Bombay
Session-4: Ultralow Power Subthreshold Analog CMOS Design for Neural Network Application by Dr Navakanta Bhat, IISc., Bangalore.
Session-5: Ultra Low-Power Design by Chandrashekhar Kypa and Christoph Heer, Infineon Technologies.
Session-6: Leakage Reduction in Low-Voltage Embedded RAMs by Dr. Kiyoo Itoh, Hitatchi, Japan.
Session-7: Techniques for Low-Power Design by C.P. Ravikumar, Texas Instruments India.
Session-8: Energy-Aware Software Design by Dr. Y.N. Srikant, IISc Bangalore.
Session-9: Leakage and Total Power Reduction at the Architectural Level by Dr. Christian Piguet, CSEM, Switzerland.