IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Event Reports - 2006
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First International Workshop on Interconnect Design and Variability
December 28-29, 2006
Golden Jubilee Hall, ECE Dept, IISc, Bangalore
Report by C.P.Ravikumar

The First International Workshop on Interconnect Design and Variability was held during Dec 28-29, 2006 in Bangalore. The workshop was organized by VSI with cooperation from IISc Bangalore and IEEE CAS Bangalore Chapter. It was attended by about 75 participants.

C.P. Ravikumar, co-chair of the workshop, welcomed the participants and explained the goals of the workshop and that of the VLSI Society of India. N.S. Nagaraj, workshop co-chair, explained the motivation for the workshop and gave an overview of the technical program. Prof. Krishna Saraswat of Stanford University inaugurated the workshop. A number of renowned experts delivered lectures at the workshop. The theme of the first day was "Interconnect Design" and the speakers who spoke included:

  • Dr. Krishna Saraswat, Stanford University, USA
  • Dr. Ram Achar, Carleton University, Canada
  • Dr. Shankar Balachandran, IIT Madras, Chennai, India
  • Vijay Sindagi, Texas Instruments, India
  • Dr. Sarma Vrudhula, Arizona State Univeristy, USA
  • Dr. Jaijeet Roychowdhury, University of Minnesota, USA
  • A panel discussion was held on the topic of "Top 5 challenging problems in Interconnect Design" where all the speakers above participated as panelists. The moderator was Dr Navakanta Bhat of the Indian Institute of Science.

    The theme of the second day of the workshop was "Variability" and the speakers included:

  • Dr. N.S. Nagaraj, Texas Instruments, India
  • Mr. Tejas Jhaveri, Carnegie Mellon University, USA
  • Dr. Dipu Pramanik, Synopsys, USA
  • Kelvin Lee, Extreme DA, USA
  • Dr. Vivek De, Intel, USA
  • A panel discussion was held on the topic of "Top 5 challenging problems in Variability" where the above speakers took part as panelists. The moderator was C.P. Ravikumar of Texas Instruments. There was lively interaction in both the panels. On both days, there was an attempt to identify some problems that Indian academia can take up for further research.

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    Three-day course on Digital Circuit Testing and Design for Testability
    August 17-19, 2006 Bangalore
    Report by C.P.Ravikumar

    The VLSI Society of India organized a three-day course on Digital Circuit Testing and Design for Testability in Bangalore during August 17-19, 2006. About 60 participants, including faculty members, students, and VLSI professionals, attended the workshop. The event was held in cooperation with IEEE Circuits and Systems Society, Bangalore Chapter. The faculty for the course included Prof. S.M. Reddy (University of Iowa, USA), Dr. Nilanjan Mukherjee (Mentor Graphics, USA), and Dr. C.P. Ravikumar (Texas Instruments, Bangalore).

    Testing of every manufactured device is necessary to ensure product quality. As the complexity of electronic integrated circuits grows, their testing has also become very complex and expensive.

    Prof. Sudhakar Reddy
    The course provided an insight into the recent trends in testing of digital circuits and designing these circuits for better testability. The course covered Logic Testing fundamentals, Advanced Fault Models, Power Aware Test, Logic BIST, Memory Test, Test Compression and Fault Diagnosis. An entire session was devoted to current industrial practices in VLSI Testing, which covered modern practices for at-speed testing, scan test compression, signal integrity issues in test and power issues in VLSI Test.

    The course covered:

  • Introduction
  • CAD tools used
  • Logic Test - Typical Fault Models
  • Advanced Faults Models
  • Design for Test
  • Logic BIST
  • Memory Test
  • Test Compression
  • Fault diagnosis
  • Industrial Case Studies
  • This course will be repeated during August 13-17, 2007 in New Delhi. Please await announcement.

    10th IEEE VLSI Design And Test Symposium - VDAT2006
    August 9-12, 2006 International Centre, Dona Paula, Goa
    Report by C.P.Ravikumar

    VDAT2006 held at International Centre, Dona Paula, Goa was attended by over 200 participants, despite the weather conditions in most part of the country. Dr. Shetye, Director, National Institute of Oceanography (NIO), Dona Paula, inaugurated the event.

    Full-day tutorials on Analog Design by Prof. K.R.K. Rao,Texas Instruments, India, and Prof. Dinesh Sharma, IIT Bombay, Low Power Electronics and Future Technologies by Prof. Vishwani Agrawal, Auburn University; D. Mukhopadhyay and P.K. Basu, Jadavpur University; Venkatesh C, Indian Institute of Science, Bangalore and Testing and Verification by Baijayanta Ray, P.K. Venkataraghavan and S. Balasubramanian, Synopsys; Indranil Sengupta, IIT Kharagpur were conducted on the first day.

    A total 48 papers, including two embedded tutorials were selected through the review process. Presentations by the participants of a two-week Custom LSI Design Workshop conducted by VLSI Society of India at Goa and student projects at VTU-VSI-ISA Confluence Meeting at Belgaum were included under the Custom Design session.

    The four-day event was interspersed with keynote speeches by Prof.M.Balakrishnan, IIT Delhi on Quality VLSI Education: A Dream, Mirage or Reality?, Rochit Rajsuman, Advantest on Future of the ATE (Open Architecture Tester); Sunit Tyagi, Intel India on Intel 65nm technology and 65nm products; Dipu Pramanik, Synopsys on Impact of layout on variability of devices for sub 90nm Technologies and N.S.Nagaraj, Texas Instruments India on Future of Interconnect in Nanometer Area.

    Panel discussions on Growing and retaining talent in VLSI with Anurag Seth, Cadence, Sunit Tyagi, Intel Tech., Nagavolu Murty, Philips India and Suhas Hiwale, Poseidon Systems as the panelists and VLSI - How long will “Advantage India” last? with Shyamal Datta, Cadence, Nagvolu Murty, Philips India were conducted.

    The event also marked the inauguration of VSI Goa Chapter, and bestowing the VLSI Education Award to Dr.Shivaling Mahant Shetti, KarMic, India for his significant contributions to the field of VLSI Education through the two-week Custom LSI Workshops he conducted at Manipal (2005) and Goa (2006).

    A good number of fellowships were granted to students and faculties with a positive feedback. The banquet dinner with a musical program added to the overall success of the event, attended by prominent VLSI professionals and academicians from India and abroad.

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    Custom LSI Design Workshop 2006
    June 1-15, 2006
    A Report by Satihish Kenkre, Controlnet India

    The VLSI Society of India organized a two-week intensive hands-on workshop Custom LSI Design (CLDW-2006) in Goa during June 1-15, 2006. The workshop was held in cooperation with Controlnet India (Goa), KarMic (Manipal), and IEEE Goa chapter. The venue of the workshop was Goa Engineering College, Farmagudi in Ponda Goa. A total of 35 candidates from academic institutions from different parts of India participated in the workshop.

    The objective of the workshop was to give the participants a complete hands-on experience of a VLSI Design project right from its conceptualization to its implementation. The participants were divided into two groups and were allotted two different problems - Audible Color and Gentle Alarm. A team leader for each group was selected from amongst the participants. The groups were guided by Mr. Kiran Damle and Mr. Vinay A B, both engineers from KarMic, under the overall guidance of Dr. S. S. Mahant-Shetti, of KarMic, Manipal.

    The workshop was inaugurated jointly by Dr. S. S. Mahant-Shetti, Prof. Dinesh Sharma, IIT - Bombay, Dr C.P. Ravikumar, Texas Instruments, Mr. P. Sridhar, Controlnet, and the Principal of Goa Engineering College, Dr.K. M. Gupt. Several technical talks were held as part of the two-week workshop - (a) Advances in VLSI Design by C.P. Ravikumar, (b) Logic Design Styles by Prof. Dinesh Sharma, (c) Introduction to Analog Design by Prof. Dinesh Sharma, (d) Design of Embedded Systems using FPGA by Mr. M. Razak, Altera,, (e) Issues in Analog Design by Kaushal Jha, Analog Devices, (f) on Verification Solutions with Big A and Big D in SoC Design by Mr. Anantha Bhat, Synopsys.

    Participants of the workshop maintained “normal” working hours beginning at 08:00 a.m. and often ending at 02:00 a.m. Dr. Mahant-Shetti along with his team was always present in the lab to solve and discuss problems and issues that came up. He provided pointers on how to conduct meetings, how to work in a team, how to freeze the size of the project so as to make it realizable in the stipulated time. This was supported by a series of lectures and tutorials by Dr. Mahant-Shetti to address the problems. The local committee comprising of Mr. P. Sridhar, Mr. Satish Kenkre, Prof. Vijay Borges and Mr. Nilesh Fal Desai took care of the local arrangements. To balance the hard work put in by the participants and the instructors, a day-trip to the pristine beaches and historical places in Goa was arranged.

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    Electronic System-level Design Workshop ESLD2006
    Jan 9-10, 2006, Bangalore
    Report by C.P.Ravikumar

    The VLSI Society of India (VSI) conducted a two-day workshop on ESL Design during Jan 9-10, 2006. The workshop was held in cooperation with IEEE Circuits and System Society, Bangalore Chapter. The event was attended by about 75 participants, who included designers, IP providers, EDA software developers, students and faculty. The workshop was held at the Golden Jubilee Hall of the Indian Institute of Science, Bangalore.

    The keynote speakers in the workshop included Prof. Arvind (Massachusetts Institute of Technology), Prof. Rajesh Gupta (UC San Diego), Mr Brian Bailey (independent consultant), and Dr Rishiyur Nikhil (CTO of Bluespec). Prof. Arvind’s talk entitled “Is Hardware Innovation Over?” began with an emphasis on the need for hardware innovation due to the innovative applications in content distribution. He argued that RTL synthesis is not the right way to design complex systems of today since they result in higher design cost and can potentially have more bugs. Due to narrow market windows of products and due to ever-changing standards and requirements, it is no more possible to manufacture large quantities of chips - just like a grocery cannot stock up a large stock of tomatoes! He gave examples of systems-on-chip designed at Sandburst and at MIT by students of a course on Design of Complex Systems to illustrate the power of the ESL paradigm. These designs used Bluespec Verilog which provides abstractions such as rules and interfaces that a computer architect can easily identify with. He illustrated how the FIFO was used as a mechanism for communicating between components and how the computation and communication were separated. He felt that when power and performance are the main concerns, ASICs are the only way and programmable solutions will be anywhere from 100x to 1000x worse in comparison.

    Dr Rajesh Gupta of UC San Diego delivered a keynote entitled “ESL: A Crucial Enabler for Platform Ownership.” He felt that ESL is not just a shift in the level of abstraction in the vertical direction, but in the horizontal direction as well - ESL is not a collection of point tools but an awareness of a new methodology that permeates all the levels of design abstraction. He felt that ESL will begin to make impact when designers can begin to do what they currently cannot do or do not do for reasons of efficiency. He illustrated some of the pain points in the design phase that ESL can and should address, such as

  • Being able to allow compositions of components
  • Ensuring correctness of compositions
  • Facilitate faster debugging
  • Enable low power designs and Power Management
  • Offer flexibility and programmability
  • Address reliability and system availability
  • Brian Bailey, an independent consultant, former CTO of Mentor Graphics, delivered a keynote talk on “ESL - What’s that?” His talk attempted to define Electronic System-level Design. He underlined the need for a taxonomy of ESL, just like Michael Flynn provided a taxonomy of computer architectures based on the number of instruction and data streams. When such a taxonomy becomes available, it becomes possible to place various solutions that are becoming available in the ESL space. Brian alluded to the book “Taxonomy of ESL” which he has coauthored with Grant Martin, where an attempt has been made to classify ESL solutions based on the starting point (software description, hardware description, algorithms) and the end point (codesign solution, RTL, codesign solution). An alternate taxonomy of ESL is based on temporal properties, data values, functional properties, and structural properties. Brian felt that having a single language for design and verification is not desirable, since the user communities are vastly different. He postulated “Bailey’s Law,” which is a corollary of Moore’s law, to state that companies must increase their productivity by 2X every year to keep pace with Moore’s law. The interest in ESL is emerging from the potential it holds for such a jump in productivity. He felt that it is natural that a workshop on ESL is being held in India, where the designers are not already ‘indoctrinated’ into the RTL-based design flow. Brian felt that SystemC has the wrong concurrency model, with threads and events as principal ways to express concurrency, which are not different from RTL. Similarly, SystemC does not scope in a resource sharing model - a SystemC programmer has to write code to control access to shared resources.

    Dr Rishiyur Nikhil of Bluespec gave a tutorial on ESLD through Bluespec System Verilog. He described a number of examples from the domain of computer architecture, such as a butterfly switch, to illustrate the power of the constructs such as “rules” (or guarded atomic actions) and “interfaces with methods”. He illustrated code written in Verilog for the same purpose can be longer and difficult to maintain when the specifications change.

    The other speakers in the workshop included Nagendra Gulur Dwarakanath (TI), Viswanath Chakrala (Wipro), Sarang Shelke (Poseidon Systems), B.P. Srinivas (Coware), Badri Gopalan (Ageia), Srinivasan Venkataramanan (Synopsys), Raghuram Tupuri (AMD), and Himanshu Sanghvi (Tensilica).

    Nagendra (TI) spoke about the absorption of ESL technologies in TI and described the experiences in using the technologies. Viswanath Chakrala (Wipro) explained the use of System C models in SoC development. Sarang Shelke (Poseidon) discussed a way to automatically compile C programs to generate software and hardware accelerator components. Srinivas (CoWare) presented virtual platforms as a means to solve the ESW dilemma of starting development only when the silicon arrives. He explained how virtual platforms could be deployed in an organization to catch architectural and functional bugs in ESW ahead of hardware availability, leading to parallelization of HW and ESW development, and consequent reduction of design cycles. Badri Gopalan gave a tutorial on System Verilog and explained how it represents an incremental step towards ESL rather than a quantum jump. Srinivasan Venkataramanan discussed the problem of system verification through System Verilog. Raghuram Tupuri explained an in-house tool used in AMD for performance modeling of microprocessors. Himanshu Sanghvi explained the power of multiprocessor SoC using configurable processors and outlined the requirements of ESL tools that can play in this market segment.

    A panel discussion moderated by Brian Bailey was held on the topic of “ESL - Dream or Reality?” The Panelists included Bill Salefsky (VP, Poseidon), Shiv Tasker (CEO of Bluespec), Prof. S.K. Nandy (IISc, Bangalore), and Pankaj (TI). Bill asked the question “Who will drive the ESL technology?” - IP vendors, application software developers, Universities, or the design community. Bill felt the system development companies will drive ESL technology and platforms will bring the next wave of advancement in ESL. He felt that processor companies, which drove the development of technologies such as formal verification, will not drive ESL. Prof. Nandy felt that the students in the Universities like to be branded as software or hardware engineers and need to be educated about system-level design. To Brian’s remark on how some US Universities are beginning to merge the Electrical Engineering and Computer Science departments to achieve this goal, Prof. Nandy replied that such a merging is desirable. Shiv felt that educating the design community about topics such as concurrency is essential for ESL to succeed. He felt that engineers are always slow in adapting new solutions; he felt that this trait must change in order to promote the use of ESL. This remark elicited a question on whether engineers will see ESL as a threat to their job security. Another question was, whether the pain of engineers has reached a level that will push them to adopt ESL. A participant said she will use new tools and technologies if they have anything new to offer. Pankaj felt that IP developers and designers are already beginning to appreciate the need for a higher level of abstraction and are beginning to use point ESL solutions. He pointed out that software is still not the important problem in a semiconductor IP company and felt that system designers must drive ESL. He felt that pulling the schedule alone cannot be the key differentiator that ESL can provide - companies care more about the performance parameters such as speed, power, and area. The question of system developers demanding a standard for ESL technologies was discussed. Although many independent, custom ESL solutions exist in design houses, the adoption of ESL will be faster when standards begin to evolve. Since some ESL technologies call for quantum leaps in the way design is done, several panelists and participants felt the need for a good fundamental understanding of concurrency, training, collaboration, partnerships, and tool support for deeper penetration of ESL.

    The entire workshop was interactive, including the keynote talks. The audience raised interesting questions and provided insightful remarks in all the talks. There were debates on the topics of functional vs behavioral level of abstraction, cycle-accurate vs cycle-approximate simulation, early estimation of power, expressive power of SystemC, and the relative merits and demerits of SystemC and System Verilog. The informal as well as formal feedback for the workshops has been excellent, and include suggestions to create a forum for regular interaction among the ESL community in India. Dr C.P. Ravikumar, secretary of VSI, thanked all the participants and the members of the organizing committee of the workshop. Special thanks are due to Suhas Hiwale and Subodh Patil of Poseidon (India), Maria Adolf (Bluespec) and Dr Bharadwaj Amruthur of Indian Institute of Science.

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